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| IRFD120 Data Sheet January 2002 1.3A, 100V, 0.300 Ohm, N-Channel Power MOSFET This advanced power MOSFET is designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. These are N-Channel enhancement mode silicon gate power field effect transistors designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. They can be operated directly from integrated circuits. Formerly developmental type TA17401. Features * 1.3A, 100V * rDS(ON) = 0.300 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information PART NUMBER IRFD120 PACKAGE HEXDIP BRAND IRFD120 Symbol D NOTE: When ordering, use the entire part number. G S Packaging HEXDIP DRAIN GATE SOURCE (c)2002 Fairchild Semiconductor Corporation IRFD120 Rev. B IRFD120 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRFD120 100 100 1.3 5.2 20 1.0 0.008 36 -55 to 150 300 260 UNITS V V A A V W W/oC mJ oC oC oC Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (See Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Measured From the Drain Lead, 2mm (0.08in) from Package to Center of Die Measured From the Source Lead, 2mm (0.08in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Device's Inductances D LD G LS S TEST CONDITIONS ID = 250A, VGS = 0V (Figure 9) VGS = VDS, ID = 250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC VDS > ID(ON) x rDS(ON) Max, VGS = 10V VGS = 20V ID = 0.6A, VGS = 10V (Figures 7, 8) VDS > ID(ON) x rDS(ON)MAX , ID = 0.6A (Figure 11) VDD = 0.5 x Rated BVDSS, ID 1.3A, VGS = 10V, RG = 9.1 RL = 38.5 for VDD = 50V MOSFET Switching Times are Essentially Independent of Operating Temperature VGS = 10V, ID = 1.3A, VDS = 0.8 x Rated BVDSS, Ig(REF) = 1.5mA (Figure 13) Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = 25V, f = 1MHz (Figure 10) MIN 100 2.0 1.3 0.9 - TYP 0.25 1.0 20 35 50 35 11 6.0 5.0 450 200 50 4.0 MAX 4.0 25 250 500 0.30 40 70 100 70 15 - UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH On-State Drain Current (Note 2) Gate Source Leakage Drain Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance Internal Source Inductance LS - 6.0 - nH Thermal Resistance Junction to Ambient RJA Free Air Operation - - 120 oC/W (c)2002 Fairchild Semiconductor Corporation IRFD120 Rev. B IRFD120 Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode G D MIN - TYP - MAX 1.3 5.2 UNITS A A S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovery Charge NOTES: VSD trr QRR TJ = 25oC, ISD = 1.3A, VGS = 0V (Figure 12) TJ = 150oC, ISD = 1.3A, dISD/dt = 100A/s TJ = 150oC, ISD = 1.3A, dISD/dt = 100A/s - 280 1.6 2.5 - V ns C 2. Pulse test: pulse width 300s, duty cycle 2%. 3. VDD = 25V, starting TJ = 25oC, L = 32mH, RG = 25, peak IAS = 1.3A. Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 Unless Otherwise Specified 1.5 ID, DRAIN CURRENT (A) 0 25 125 50 75 100 TA , AMBIENT TEMPERATURE (oC) 150 1.2 0.9 0.6 0.4 0.6 0.2 0 0.3 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE 10 20 VGS = 10V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 9V VGS = 8V 12 VGS = 7V 8 VGS = 6V 4 VGS = 5V VGS = 4V 0 100 0 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) 50 ID, DRAIN CURRENT (A) 1 100s 1ms 10ms 0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 100ms 0.01 TJ = MAX RATED 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) DC 0.1 FIGURE 3. FORWARD BIAS SAFE OPERATING AREA ID, DRAIN CURRENT (A) 16 FIGURE 4. OUTPUT CHARACTERISTICS (c)2002 Fairchild Semiconductor Corporation IRFD120 Rev. B IRFD120 Typical Performance Curves 10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V VGS = 9V 6 VGS = 6V Unless Otherwise Specified (Continued) IDS(ON), DRAIN TO SOURCE CURRENT (A) 20 VGS = 8V VGS = 7V ID, DRAIN CURRENT (A) 8 16 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS > ID(ON) x rDS(ON)MAX 12 TJ = -55oC oC TJ = 25 TJ = 125oC 4 VGS = 5V 2 VGS = 4V 0 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 8 4 0 0 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS 0.8 2s PULSE TEST NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE () 2.2 0.6 VGS = 10V 1.8 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 0.6A 1.4 0.4 1.0 0.2 VGS = 20V 0.6 0 0.2 0 10 20 30 ID, DRAIN CURRENT (A) 40 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) NOTE: Heating effect of 2s pulse is minimal. FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 1.25 IDS = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.15 C, CAPACITANCE (pF) 1000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 800 1.05 600 CISS 400 COSS CRSS 0.95 0.85 200 0.75 -40 0 40 80 120 160 0 0 10 TJ , JUNCTION TEMPERATURE (oC) 30 40 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 50 FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE (c)2002 Fairchild Semiconductor Corporation IRFD120 Rev. B IRFD120 Typical Performance Curves 5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX Unless Otherwise Specified (Continued) 2 ISD, SOURCE TO DRAIN CURRENT (A) TJ = -55oC TJ = 25oC TJ = 125oC PULSE DURATION = 80s gfs, TRANSCONDUCTANCE (S) DUTY CYCLE = 0.5% MAX 102 5 2 10 5 2 0.1 TJ = 150oC TJ = 25oC 4 3 2 1 0 0 4 8 12 ID , DRAIN CURRENT (A) 16 20 0 1 2 3 VSD, SOURCE TO DRAIN VOLTAGE (V) 4 FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE 20 ID = 5.2A VGS, GATE TO SOURCE (V) VDS = 20V VDS = 50V VDS = 80V 10 15 5 0 0 2 4 6 QG, GATE CHARGE (nC) 8 10 FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + - 0V IAS 0.01 0 tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS (c)2002 Fairchild Semiconductor Corporation IRFD120 Rev. B IRFD120 Test Circuits and Waveforms (Continued) tON td(ON) tr RL VDS + tOFF td(OFF) tf 90% 90% RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 16. SWITCHING TIME TEST CIRCUIT VDS (ISOLATED SUPPLY) FIGURE 17. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS 12V BATTERY 0.2F 50k 0.3F G DUT 0 Ig(REF) 0 IG CURRENT SAMPLING RESISTOR S VDS ID CURRENT SAMPLING RESISTOR Ig(REF) 0 FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS (c)2002 Fairchild Semiconductor Corporation IRFD120 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM DISCLAIMER FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R) SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R) VCXTM STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4 |
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